A typical semiconductor device in a complementary metal-oxide-semiconductor (CMOS) circuit is formed in a p-well or an n-well in a semiconductor substrate. Since other semiconductor devices are also present in the semiconductor substrate, the semiconductor device requires electrical isolation from adjacent semiconductor devices. Electrical isolation is typically provided by isolation structures that employ trenches filled with an insulator material. Electrical isolation of the semiconductor device from other devices located in the same well is called “intra-well isolation.” Electrical isolation of the semiconductor device from other devices in an adjacent well of the opposite type is called “inter-well isolation.” In both cases, unintended functionality of parasitic devices, such as parasitic pnp or npn bipolar transistors, formed by various elements of the semiconductor device and adjacent semiconductor devices, needs to be suppressed by placing dielectric material, typically in the form of trench isolation structures, in the current paths among the elements of the parasitic devices.
Referring to FIG. 1, a vertical cross-sectional view of a prior art trench isolation structure having minimum separation distances between adjacent device regions shows an inter-well trench isolation structure 4, and two intra-well trench isolation structures 6. The inter-well isolation structure 4 is located at a boundary between the p-well 11 and the n-well 12, and is bounded by a pair of substantially vertical first trench sidewalls 66 and a substantially horizontal first trench bottom surface 67. One of the intra-well trench isolation structures 6 is located within a p-well 11, and is bounded by a pair of substantially vertical intra-well trench sidewalls 16 and one of substantially horizontal intra-well trench bottom surfaces 17. The other of the intra-well trench isolation structures 8 is located within an n-well 12, and is bounded by the other pair of substantially vertical intra-well trench sidewalls 16 and the other of the substantially horizontal intra-well trench bottom surfaces 17. The various isolation structures (4, 6) comprise the same dielectric material.
The depths of the inter-well trench isolation structure 4 and the intra-well trench isolation structures 6 are substantially the same. Variations between the various depths of the trench isolation structures (4, 6), that is, variations in the heights of inter-well trench sidewalls 66 and intra-well trench sidewalls 16 are typically caused by process bias between trenches having different widths during a reactive ion etch of the trenches. Therefore, the inter-well trench bottom surface 67 and the intra-well trench bottom surfaces 17 are substantially at the same depth from a top surface of the semiconductor substrate 8.
Both the p-well 11 and the n-well 12 are located above a substrate layer 10′, which typically has the same doping level as the original semiconductor substrate prior to the doping of the wells (11, 12). Typically, at least one heavily n-doped region 91, such as source and drain regions of an n-type field effect transistor, is located above the p-well 11, and at least one heavily p-doped region 92, such as source and drain regions of a p-type field effect transistor, is located above the n-well 12. The at least one heavily n-doped region 91, the at least one heavily p-doped region 92, the p-well 11, the n-well 12, the two intra-well trench isolation structures 6, the inter-well trench isolation structure 4, and the substrate layer 10′ are located within a semiconductor substrate 8.
The well boundary 13 between the p-well 11 and the n-well 12 is determined by the location of the edge of a patterned p-well block mask (not shown) during a p-well implantation process and by the location of the edge of a patterned n-well block mask (not shown) during an n-well implantation process. While having coincident two edges of the block masks is ideal, the probability of occurrence of such an event is statistically insignificant since alignment of each block mask involves alignment tolerances, or overlay errors. The well boundary 13 is typically formed in the middle of the edge of the patterned p-well block mask and the edge of the patterned n-well mask. Statistically, the well boundary 12 may be located anywhere between two limits A and B, which are defined by a maximum variation of the overlay of the two edges of the block masks. The distance between the two limits define the range ROL of the well boundary 13, which is typically on the order of about 30 nm for a mid-ultraviolet (MUV) lithography. Calculation of the minimum width of the inter-well isolation trench structure 4 in a semiconductor circuit design needs to factor in this variation to insure that the worst case inter-well isolation distances provide sufficient inter-well isolation to semiconductor devices located nearby.
An inter-well trench minimum width w1_p of the inter-well trench isolation structure 4 is determined by a combination of the depth of the inter-well trench isolation structure 4 (which is the same as the height of the inter-well trench isolation sidewalls 66), the depths of the at least one heavily n-doped region 91 and the at least on heavily p-doped region 92, the doping levels of the p-well 11 and the n-well 12, the overlay tolerances of lithography processes that are used to form the two wells (11, 12), and the operating voltages of the semiconductor devices abutting the inter-well trench isolation structure 4. An intra-well trench minimum width w2_p of the intra-well trench isolation structures 6 is determined by a combination of the depth of the intra-well trench isolation structures 6, the depth of the at least one heavily n-doped region 91 or the at least one heavily n-doped region 92, the doping level of the p-well 11 or the n-well 12, and the operating voltages of the semiconductor devices abutting the intra-well trench isolation structure 6.
The paths of the weakest inter-well isolation in the prior art isolation structure are represented by a prior art heavily n-doped region to n-well separation distance d2p—p and a prior art heavily p-doped region to p-well separation distance d2n—p in FIG. 1. Likewise, the path of the weakest intra-p-well isolation in the prior art isolation structure is represented by a prior art heavily n-doped region to another heavily n-doped region separation distance d1p—p. The path of the weakest intra-n-well isolation in the prior art isolation structure is represented by a prior art heavily p-doped region to another heavily p-doped region separation distance d1n—p. From geometrical considerations, the inter-well trench minimum width w1_p needs to be greater than the intra-well trench minimum width w2_p due to the presence of the boundary between the p-well 11 and the n-well 12 near the middle of the inter-well trench isolation structure 4.
For example, the depths of the at least one heavily n-doped region 91 and the at least one heavily p-doped region 92 may be about 80 nm, the depths of the various trench isolation structures (4, 6) may be about 280 nm, and the overlay tolerance of lithography processes for ion implantations well definition may be about 30 nm. For 1.1V operation of semiconductor devices, this requires the inter-well trench minimum width w1_p to be about 208 nm such that each of the prior art heavily n-doped region to n-well separation distance d2p—p and the prior art heavily p-doped region to p-well separation distance d2n—p is at least 289 nm. The prior art heavily n-doped region to another heavily n-doped region separation distance d1p—p exceeds twice the difference between the depth of the intra-well trench isolation structure 6 and the depth of the heavily n-doped region 91, and consequently exceeds 400 nm. The intra-well trench minimum width w2_p may be limited not by intra-well device isolation considerations, but by process capability considerations to insure filling of the intra-well trench isolation structures 6 with a dielectric material. Considerations on the prior art heavily p-doped region to another heavily p-doped region separation distance d1n—p produces the same result.
Further, the prior art trench isolation structure provides substantially the same depth between the inter-well isolation structure 4 and the intra-well isolation structures 6. Since gap fill characteristics during deposition of dielectric material in a trench depends on the aspect ratio of the trench structure to be filled, a wider trench may have a deeper depth and still be filled. An extended depth would be preferred on an inter-well trench isolation structure having a greater width in this case.
Therefore, there exists a need for an inter-well isolation structure having an extended depth compared to the depth of an intra-well isolation structure having a narrower width and methods of manufacturing the same.
Further, there exists a need for an inter-well trench isolation structure having reduced minimum width compared to the prior art and methods of manufacturing the same.
In addition, there exists a need for such an inter-well trench isolation structure that requires minimal additional processing steps in terms of cost and complexity during the manufacturing.